Method of modular reduction and modular reduction circuit
US5793659A · kind A · utility
15Cited by
8References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 15, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Oct 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of modular reduction P mod Q based on a precomputation. Two quantities are precomputed and stored in a look-up table. Based on these stored precomputed quantities, two stages of partial modular reduction are performed. The result of the second stage of partial modular reduction is then adjusted according to the value of Q, to determine the modular reduction result. The modular reduction result may be provided to variable radix multiplication logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.