Parallel-processor graphics architecture
US5794016A · kind A · utility
148Cited by
12References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 11, 1995 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Dec 11, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel-processor graphics architecture appropriate for multimedia graphics workstations that is scalable to the needs of a user. The graphics architecture includes one or more rendering processors and a graphics memory that is partitioned into blocks. Noncontiguous groups of the blocks are then assigned to different processors. The parallel-processor graphics architecture is scalable by the number of rendering processors utilized, and is configurable with respect to the allocation of the groups of the blocks to specific rendering processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.