Method and system for dynamically recovering a register-address-table upon occurrence of an interrupt or branch misprediction
US5794024A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1996 |
| Grant date | Aug 11, 1998 |
| Priority date | — |
| Expiry date | Mar 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.