Integrated pad and fuse structure for planar copper metallurgy
US5795819A · kind A · utility
37Cited by
9References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Sep 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor interconnection consists of a corrosion resistant integrated fuse and Controlled, Collapse Chip Connection (C4) structure for the planar copper Back End of Line (BEOL). Non copper fuse material is directly connected to copper wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.