Memory cells with a reduced area capacitor interconnect and methods of fabrication therefor
US5796134A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Feb 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
Abstract
A memory cell is formed including an insulation region on the substrate and a transistor including a gate on the substrate and a source/drain region in the substrate disposed between the gate and the insulation region. The cell also includes a capacitor including an electrode overlying the insulation region, the electrode having a lateral surface adjacent the source/drain region. A conductive interconnecting region is formed on the substrate and extends from the source/drain region to contact the lateral surface of the first electrode of the capacitor. The capacitor may include a first electrode on the insulation region, a dielectric region on the first electrode, and a second electrode on the dielectric region. The first electrode preferably is platinum and the dielectric region preferably is a ferroelectric material such as lead zirconate titanate (PZT) or Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST). The first electrode preferably has a lateral surface, and the conductive interconnecting region extends to contact the lateral surface of the first electrode. The first electrode preferably has a top surface adjacent the lateral surface, and the cell preferably further comprises an insulatio…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.