"Physical design automation system and process for designing integrated circuit chip using simulated annealing with ""chessboard and jiggle"" optimization"
US5796625A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Mar 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.