Ivan Pavisic
55Patents
16h-index
34Co-inventors
80Inventor score
Filing activity: Mar 1, 1996 → Oct 11, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6182272A | Metal layer assignment | Physics | 217 | Expired |
| US7093228B2 | Method and system for classifying an integrated circuit for optical proximity correction | Physics | 208 | Expired |
| US6067409A | Advanced modular cell placement system | Physics | 114 | Expired |
| US6412102B1 | Wire routing optimization | Physics | 108 | Expired |
| US5898597A | Integrated circuit floor plan optimization system | Physics | 101 | Expired |
| US6292929A | Advanced modular cell placement system | Physics | 100 | Expired |
| US6068662A | Method and apparatus for congestion removal | Physics | 94 | Expired |
| US6123736A | Method and apparatus for horizontal congestion removal | Physics | 86 | Expired |
| US6058254A | Method and apparatus for vertical congestion removal | Physics | 85 | Expired |
| US6070108A | Method and apparatus for congestion driven placement | Physics | 50 | Expired |
| US6550045B1 | Changing clock delays in an integrated circuit for skew optimization | Physics | 49 | Expired |
| US6550044B1 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Physics | 31 | Expired |
| US6546541B1 | Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances | Physics | 30 | Expired |
| US6546539B1 | Netlist resynthesis program using structure co-factoring | Physics | 23 | Expired |
| US6941533B2 | Clock tree synthesis with skew for memory devices | Physics | 19 | Expired |
| US6038385A | "Physical design automation system and process for designing integrated circuit chip using ""chessboard"" and ""jiggle"" optimization" | Physics | 19 | Expired |
| US6637016B1 | Assignment of cell coordinates | Physics | 16 | Expired |
| US6269469A | Method and apparatus for parallel routing locking mechanism | Physics | 14 | Expired |
| US6487697B1 | Distribution dependent clustering in buffer insertion of high fanout nets | Physics | 13 | Expired |
| US6629304B1 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Physics | 12 | Expired |
| US5796625A | "Physical design automation system and process for designing integrated circuit chip using simulated annealing with ""chessboard and jiggle"" optimization" | Physics | 12 | Expired |
| US6557144B1 | Netlist resynthesis program based on physical delay calculation | Physics | 10 | Expired |
| US6075933A | Method and apparatus for continuous column density optimization | Physics | 10 | Expired |
| US7096442B2 | Optimizing IC clock structures by minimizing clock uncertainty | Physics | 9 | Expired |
| US7356785B2 | Optimizing IC clock structures by minimizing clock uncertainty | Physics | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.