Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein
US5796638A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 24, 1996 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Jun 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance. Corners in representations of adjacent power rails are also detected, where these representations have opposing edges separated by a minimum rail spacing, and a position of at least one of the power rails relative to the other i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.