Method and apparatus for self-snooping a bus during a boundary transaction
US5797026A · kind A · utility
31Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | Sep 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.