Repairable wafer scale integration system
US5798565A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1995 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Jan 23, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus for integrating wafer scale semiconductor integrated circuits and interfacing them with other systems. A wafer, partial wafer, die or plurality of same are mated to a printed circuit board (PCB) which electrically contacts the pads on each die using small conductive pillars. The PCB in turn is connected easily to other electronic systems. The entire apparatus is incorporated into other systems which utilize the dice in the apparatus. The apparatus may be fitted with heating elements and cooling channels to generate the necessary dice temperatures for burn-in, testing, and operation. The apparatus is easily adaptable to include more dice in a stacked configuration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.