Dynamic random access memory having no capacitor and method for fabricating the same
US5798965A · kind A · utility
54Cited by
5References
2Claims
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Key dates
| Filing date | Sep 5, 1996 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Sep 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A capacitor-less dynamic random access memory (DRAM) having a unit cell includes a first transistor receiving data through a source electrode connected to a bit line according to a signal level applied to a gate electrode, and a second transistor storing charges corresponding to data input to the first transistor and outputting a reference voltage to the bit line according to the level of the charges. This improves the reliability and integration of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.