Sensing scheme for non-volatile memories
US5798967A · kind A · utility
42Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1997 |
| Grant date | Aug 25, 1998 |
| Priority date | — |
| Expiry date | Feb 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sensing circuit charges the bit lines of an associated memory array using one or more large-area pass transistors during reading operations of a selected memory cell of the memory array. In this manner, the read speed of the memory array is independent of the channel current of the memory cell. A sink transistor sinks a constant current from the selected bit line during reading to improve the noise margin of the sensing circuit so that memory arrays associated with the sensing circuit do not require the reference bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.