Method for manufacturing diffused channel insulated gate effect transistor
US5801078A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Dec 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
A diffused channel insulated gate field effect transistor comprised of a gate isolation layer and a gate electrode positioned on an upper surface of a semiconductor substrate of a first conductivity type; a body region of a second conductivity type present in the semiconductor substrate lying below a part of the gate electrode, on at least one side thereof, and extending downwards to a first depth; a source region of said first conductivity type present in the body region, spaced away from the first end of the gate electrode, at the upper surface and extending downwards therefrom to a second depth, shallower than the first depth; and a lightly doped region of the first conductivity type present in the body region, at least partly between the source region and the gate electrode, extending downwards to a substantially shallower depth than the second depth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.