Depletion mode pass gates with controlling decoder and negative power supply for a programmable logic device
US5801551A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Aug 1, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Depletion mode pass gates utilized in a PLD to enable a gate voltage of Vcc to be applied for turn off, as opposed to a higher voltage required for enhancement type devices. With Vcc applied for turn off, gate oxide stress is reduced and chip reliability increased. A decoder utilizing PMOS transistors is further used to supply a negative gate voltage to enable turn off of the depletion mode pass gates. In one embodiment, to prevent pumping the power supply voltage above Vcc when supplying Vcc to gates of the pass gates, the decoder is an all PMOS device using PMOS transistors to connect Vcc to gates of the pass gates. In another embodiment both NMOS and PMOS transistors are utilized, with PMOS blocking transistors utilized to prevent a negative voltage from being applied to the NMOS transistors and causing current leakage. A negative voltage pump is further provided to supply a sufficient negative voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.