Precise delay line circuit with predetermined reset time limit
US5801568A · kind A · utility
2Cited by
11References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 1995 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Dec 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay line circuit is provided that precisely delays the incoming referenced clock signal by utilizing two delay cells and a sample-and-hold circuit. The circuit eliminates the need for sensing circuitry at the output to determine if the need to monitor the delay line circuit is operating in an undesirable operation. By eliminating the sensing circuitry the reliability of delay line circuit is significantly increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.