Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms
US5802330A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters includes an arbitration feedback control circuit and feedback register for generating and storing a value to indicate whether the latency in obtaining the bus during a previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or the latency in obtaining the bus reached a near-critical point). If the value in the feedback register of a particular peripheral indicates the master desires faster access to the bus, an arbitration control unit of the bus arbiter increases a level of arbitration priority gi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.