Configurable drive clock
US5802356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Nov 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method which provides specified hold times for communication signals transmitted from a processing device that is capable of operating at different frequencies, to external devices, is provided. The apparatus includes a clock multiplier which generates an internal clock signal which is a multiple of an external clock, a ring oscillator, which provides a number of outputs of the same frequency as the internal clock, but at fixed phase offsets from the internal clock, and clock select circuitry, which selects one of the outputs from the ring oscillator, depending on the speed of the internal clock, to be used as a drive clock signal for a bus unit. Selection of one of the phase offset outputs provides for a specified hold time regardless of the internal clock speed of the processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.