Mechanism for writing back selected doublewords of cached dirty data in an integrated processor
US5802559A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Nov 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated processor is provided that includes a cache controller which keeps track of a physical address in the system memory which corresponds to each entry within the cache memory. The address tag and state logic circuit further contains state information consisting of a dirty bit allocated for each doubleword (or word) within each line as well as a valid bit for each line. The dirty bit allocated for each doubleword indicates whether that doubleword is dirty or clean, and the valid bit for each line indicates whether the line is valid or invalid. The cache controller further includes a snoop write-back control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master on the local bus. During such a memory cycle of an alternate bus mater, a comparator circuit determines whether a cache hit has occurred. If a cache hit occurs and one or more dirty doublewords are contained within the corresponding line, the snoop write-back control circuit initiates a snoop write-back cycle to write-back only those doublewords within the line that is marked dirty. If two or more doublewords within the hit cache line are marked dirty, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.