Multibus cached memory system
US5802560A · kind A · utility
107Cited by
7References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 1995 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Aug 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.