Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory
US5802571A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1996 |
| Grant date | Sep 1, 1998 |
| Priority date | — |
| Expiry date | Oct 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests. The age-based arbitration scheme can also be used for multiple cache accesses occurring in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.