Method of fabricating high .beta.HBT devices
US5804487A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Jul 10, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
Abstract
A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa. The sacrificial layer is stripped using an isotropic etch leaving a base ohmic metal region surrounding an emitter mesa at a spacing that is determined by the initial undercut of the sacrificial laye…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.