Transistor ratio controlled CMOS transmission line equalizer
US5805031A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Sep 3, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/144
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A CMOS transmission line equalizer is provided for receiving distorted signals transmitted through a transmission line and for compensating for the signal distortion. The equalizer has a transfer function characteristic with a single pole and a single zero. The transfer function includes a mirroring ratio circuit (CMR) for controlling the ratio between the single pole and the single zero. The mirroring ratio circuit is controlled by transistor size ratio. The single zero serves to cancel the dominant pole in the transfer function of the transmission line so as to compensate for the signal distortion caused by the transmission line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.