Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture
US5805475A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1997 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Mar 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point numbers load-store unit includes a translator for converting between the single-precision and double-precision representations, and Special-Case logic for providing Special-Case signals when a store is being performed on zero, infinity, or NaN. A store-float-double instruction is executed by concatenating a suffix to the mantissa in the single-precision floating-point register and replacing the high-order bit of the exponent with a prefix selected as a function of the high-order bit, wherein the resulting mantissa and exponent form a double-precision floating-point number that is then stored to memory. A load-float-double instruction is executed by dropping the suffix from the mantissa of the double-precision floating-point number in memory, and replacing the prefix with the high-order bit, wherein the resulting mantissa and exponent form a single-precision floating-point number that is then loaded into the single-precision floating-point register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.