Lee Evan Eisen
55Patents
12h-index
78Co-inventors
87Inventor score
Filing activity: Feb 10, 1995 → Oct 16, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5805475A | Load-store unit and method of loading and storing single-precision floating-point registers in a double-precision architecture | Physics | 56 | Expired |
| US7194645B2 | Method and apparatus for autonomic policy-based thermal management in a data processing system | Physics | 55 | Expired |
| US9672043B2 | Processing of multiple instruction streams in a parallel slice processor | Physics | 29 | Active |
| US9690586B2 | Processing of multiple instruction streams in a parallel slice processor | Physics | 27 | Active |
| US9665372B2 | Parallel slice processor with dynamic instruction stream mapping | Physics | 25 | Active |
| US9690585B2 | Parallel slice processor with dynamic instruction stream mapping | Physics | 23 | Active |
| US6442675B1 | Compressed string and multiple generation engine | Physics | 22 | Expired |
| US6345356B1 | Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs | Physics | 18 | Expired |
| US5619408A | Method and system for recoding noneffective instructions within a data processing system | Physics | 18 | Expired |
| US5790445A | Method and system for performing a high speed floating point add operation | Physics | 18 | Expired |
| US6286094A | Method and system for optimizing the fetching of dispatch groups in a superscalar processor | Physics | 14 | Expired |
| US5678016A | Processor and method for managing execution of an instruction which determine subsequent to dispatch if an instruction is subject to serialization | Physics | 12 | Expired |
| US5897654A | Method and system for efficiently fetching from cache during a cache fill operation | Physics | 10 | Expired |
| US6321380A | Method and apparatus for modifying instruction operations in a processor | Physics | 8 | Expired |
| US6848044B2 | Circuits and methods for recovering link stack data upon branch instruction mis-speculation | Physics | 8 | Expired |
| US7769984B2 | Dual-issuance of microprocessor instructions using dual dependency matrices | Physics | 8 | Active |
| US6385719B1 | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor | Physics | 8 | Expired |
| US6098168A | System for completing instruction out-of-order which performs target address comparisons prior to dispatch | Physics | 8 | Expired |
| US9977678B2 | Reconfigurable parallel execution and load-store slice processor | Emerging Cross-Sectional Technologies | 7 | Active |
| US6336182B1 | System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch | Physics | 6 | Expired |
| US7890738B2 | Method and logical apparatus for managing processing system resource use for speculative execution | Emerging Cross-Sectional Technologies | 6 | Active |
| US8683180B2 | Intermediate register mapper | Physics | 6 | Active |
| US5809323A | Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor | Physics | 6 | Expired |
| US9971602B2 | Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices | Emerging Cross-Sectional Technologies | 6 | Active |
| US9141421B2 | Reducing power grid noise in a processor while minimizing performance loss | Emerging Cross-Sectional Technologies | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.