Efficient technique for implementing broadcasts on a system of hierarchical buses
US5805839A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Jul 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/173
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for a multiprocessor computer system is provided. The multiprocessor computer system includes multiple repeater nodes. Each repeater node includes a transaction repeater and at least one bus device coupled to the repeater on a lower level bus. The repeater nodes are connected by an upper level bus. Each bus device includes an incoming queue. Transaction originating in a particular repeater node are stored in the incoming queue, whereas transactions originating in other repeater nodes bypass the incoming queue to the bus device. A control signal is asserted by the repeater so that a transaction is received by bus devices in the originating node from the incoming queues at the same time and in the same order it is received by bus devices in non-originating nodes. Thus a hierarchical bus structure is provided that overcomes physical/electrical limitations of single bus architecture while maximizing bus bandwidth utilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.