Digital simulator circuit modifier, network, and method
US5805859A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed. Once the normal simulation events have been executed, the defer events are executed which permits the inputs of the state elements to change after other simulation events have been executed, thereby ensuring consistent evaluation of pin changes at state ele…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.