In a pipelined processor, setting a segment access indicator during execution stage using exception handling
US5805879A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Feb 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a pipelined processor having at least one execution pipeline for executing instructions, the execution pipeline including ID (decode), AC (address calculation), and EX (execution) processing stages, the processor capable of addressing segments of system memory coupled thereto, a circuit for, and method of, setting a segment access indicator associated with a segment of the system memory being accessed by the processor. The circuit includes: (a) exception generating circuitry to generate an exception when the segment access indicator requires setting and (b) exception handling circuitry, invoked by the processor in response to generation of the exception, to flush the execution pipeline of instructions following a segment load instruction, set the segment access indicator and load an address pointer of the processor with an address corresponding to a specified location within the segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.