Arithmetic logic unit with conditional register source selection
US5805913A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 1993 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Nov 30, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30101
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero. The instruction word may designate one or more of these status bits not changed by the current instruction. The data registers (200) are preferably accessed via consecutive register numbers, the first register havin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.