Reduced mask DRAM process
US5808335A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 1997 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Jul 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A DRAM device structure, using a stacked capacitor configuration, has been developed. The stacked capacitor structure is comprised of a lower, polysilicon storage node, a thin composite dielectric layer, and an overlying capacitor plate, comprised of a composite layer of an overlying polysilicon layer, on a thin amorphous silicon layer, contacting an N type source and drain region, in a semiconductor substrate. A bit line contact structure, comprised of a metal silicide - polysilicon composite structure, is also used in the DRAM device structure. A PFET device, adjacent to the stacked capacitor DRAM device, featuring a two part contact structure, to P type source and drain regions, comprised of a wide top, aluminum - copper shape, overlying a narrower tungsten stud, is also used in this invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.