Clock clamping circuit that prevents clock glitching and method therefor
US5808485A · kind A · utility
2Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 5, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Aug 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for clamping a clock signal line that prevents clock glitching is disclosed. The system is comprised of a plurality of logic gates which generates a signal to clamp the clock signal line only on the occurrence of the clock signal line being low, a clock clamping signal 26 is generated indicating that a peripheral device wants to clamp the clock signal line, and a start condition is detected indicating that the clock signal line may be clamped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.