Memory system which enables storage and retrieval of more than two states in a memory cell
US5808932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.