Memory array comprised of multiple FIFO devices
US5809557A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1997 |
| Grant date | Sep 15, 1998 |
| Priority date | — |
| Expiry date | Jan 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output. Each read pointer register corresponds to one of the N FIFOs, each read pointer register holding the read address corresponding to one of the N FIFOs. The read multiplexer has N read inputs, a read output and a read select input, the N read inputs bein…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.