Process for reflow bonding a semiconductor die to a substrate and the product produced by the product
US5811317A · kind A · utility
37Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 1995 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Aug 25, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for assembly of bare silicon die onto flexible or thin laminate substrates that minimizes substrate and die warpage induced after underfill cure operations and at the same time reduces the cycle time for the assembly process. More specifically, an opposing layer of thermoset component is adhered to a balance plate (metal) or other material with applicable coefficient of thermal expansion "CTE" and modulus of elasticity on the top of the die. The offsetting layer of material causes the die to warp to the other side and as a result the two self opposing warpage effects neutralize themselves.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.