Wafer cleaning procedure useful in the manufacture of a non-volatile memory device
US5811334A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer surface cleaning method is provided comprising immersion of the wafer in a H.sub.2 O:NH.sub.4 OH:H.sub.2 O.sub.2 solution at a temperature less than 65.degree. C. prior to formation of a thin oxide such as a tunnel oxide or gate oxide. Immersion of the wafer in a sub-65.degree. C. NH.sub.4 OH results in a smoother wafer surface that increase the charge-to-breakdown (Q.sub.BD) of the subsequently formed oxide. In the tunnel oxide embodiment, the lower temperature solution also reduces the oxide etch rate of the solution enabling a minimum overgrowth of gate oxide which, in turn, enables the addition of an in situ growth temperature anneal of the gate oxide without altering other process parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.