Block clock and initialization circuit for a complex high density PLD
US5811987A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Nov 5, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.