Mesh planes for multilayer module
US5812380A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Jan 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer module for packaging at least one electronic component 50. The module includes a plurality of thickfilm layers, and a wiring structure 45 to permit the connection of on-module capacitors. The multilayer module is fabricated such that the wiring structure includes a partial mesh plane 46, 47, 48, and 49 between the topmost and second topmost layers of the thickfilm. Logic noise is reduced in the multilayer module by maximizing the mutual inductance between adjacent mesh planes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.