Redundancy memory register
US5812467A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Apr 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy memory register for storing defective addresses of defective memory elements in a memory device includes a plurality of memory units each one storing a respective defective address bit and comparing the defective address bit stored therein with a respective current address bit of a current address supplied to the memory device. The register includes a first group of memory units and a second group of memory units storing a first defective address, and a third group of memory units storing, together with the first group, a second defective address which has an address part in common with the first defective address. The first and second group of memory units supply first redundancy selection means for selecting a first redundancy memory element when the current address coincides with the first defective address. The first and third group of memory units supply second redundancy selection means for selecting a second redundancy memory element when the current address coincides with the second defective address. The register comprises first address configuration detection means for detecting if the current address coincides with a default configuration stored in the first…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.