Method and apparatus for testing multi-port memory
US5812469A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Dec 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.