Nested loop method of identifying synchronous memories
US5812472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.