Digital receiver using a concatenated decoder with error and erasure correction
US5812603A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1996 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Aug 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.