Digital hardware architecture for realizing neural network
US5812993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1997 |
| Grant date | Sep 22, 1998 |
| Priority date | — |
| Expiry date | Feb 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital neural network architecture including a forward cascade of layers of neurons, having one input channel and one output channel, for forward processing of data examples that include many data packets. Backward cascade of layers of neurons, having one input channel and one output channel, for backward propagation learning of errors of the processed data examples. Each packet being of a given size. The forward cascade is adapted to be fed, through the input channel, with a succession of data examples and to deliver a succession of partially and fully processed data examples each consisting of a plurality of packets. The fully processed data examples are delivered through the one output channel. Each one of the layers is adapted to receive as input in its input channel a first number of data packets per time unit and to deliver as output in its output channel a second number of data packets per time unit. The forward cascade of layers is inter-connected to the backward cascade of layers by means that include inter-layer structure, such that, during processing phase of the forward cascade of neurons, any given data example that is fed from a given layer in the forward cascade t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.