Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
US5814858A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.