Bimodal ESD protection for DRAM power supplies and SCRs for DRAMs and logic circuits

US5814865A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Charvaka Duvvury · Plano, US
• Michael Chaine · Boise, US

Key dates

• Filing date: Oct 31, 1996
• Grant date: Sep 29, 1998
• Expiry date: Oct 31, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and wherein the diode and the transistor (106) are connected between the first terminal and the second terminal, the diode protects the transistor and the circuit during the negati…