Receiver input voltage protection circuit
US5815354A · kind A · utility
11Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 1997 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An off-chip receiver circuit for interfacing an integrated circuit of a 2.5 Volt CMOS technology to a 3.3 Volt LVTTL bus. The off-chip receiver includes protection circuitry for preventing overstressing of the gate oxide caused by undershoot/overshoot peaks of -1 volt to 6 volts on the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.