Microprocessor arithmetic logic unit using multiple number representations
US5815420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor (5) having at least one arithmetic logic unit, or ALU, (42) for operating upon operands of multiple number representation types is disclosed. The ALU (42) includes a binary logical unit (52) for performing logical operations upon operands in a binary representation, and an arithmetic unit (50, 50') for performing arithmetic operations upon operands in a redundant number representation. The redundant number representation is of a type that may be operated upon by adder circuitry such as signed-digit adders or carry-save adders, where carry information need not propagate along the entire operand. A register file (39, 39') is provided, which stores each operand in both the binary form and in the redundant number representation; a valid bit (V) is provided in combination with the binary portion of each entry in the register file (39, 39'). Upon execution of a logical operation, the result is written back into the register file (39, 39') in both the binary and redundant forms, setting the valid bit to indicate that the binary form is valid. Upon execution of an arithmetic instruction, the binary form of the result is not immediately available; the redundant representati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.