Memory device having complete row redundancy
US5815447A · kind A · utility
28Cited by
7References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 8, 1996 |
| Grant date | Sep 29, 1998 |
| Priority date | — |
| Expiry date | Aug 8, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An ATM switch including a multi-port memory is described. The multi-port memory has a dynamic random access memory (DRAM) and input and output serial access memories (SAMs). The multi-port memory includes an array of primary and redundant memory cells. Data transfer buses are described which traverse the array and can be coupled to either the primary or redundant memory cells. Redundant row enable circuitry is described which enables an entire row of redundant memory cells to be substituted for any row of primary memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.