High-yield methods of fabricating large substrate capacitors
US5817533A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/22
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described are methods of manufacturing large substrate capacitors for multi-chip module applications and the like using procedures compatible with common semiconductor fabrication procedures. A capacitor is formed where the top electrode thereof is divided into a plurality of segmented pads which are initially electrically isolated from one another. Each segmented pad forms a capacitor with the underlying dielectric layer and bottom capacitor electrode. Each segmented capacitor is electrically tested, and defective ones are identified. A conductive layer is thereafter formed over the segmented pads such that the conductive layer is electrically isolated from the pads of defective capacitors. The conductive layer electrically couples the good capacitors in parallel to form a high-value bypass capacitor which has low parasitic inductance. Large embedded MCM bypass capacitors can thereby be fabricated with minimal impact to the overall manufacturing yield. Novel testing methods within a scanning electron microscope environment are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.