Process of making a MOS-technology power device

US5817546A · kind A · utility

Assignees

• STMicroelectronics SA
• Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno · IT

Inventors

• Giuseppe Ferla · Catania, IT
• Ferruccio Frisina · Gravina di Catania, IT

Key dates

• Filing date: Dec 19, 1995
• Grant date: Oct 6, 1998
• Expiry date: Dec 19, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/126

Abstract

A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. A dopant of the first conductivity type is then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.