Process of making a dram cell arrangement

US5817552A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Roesner · Austin, US
• Lothar Risch · Neubiberg, DE
• Franz Hofman · Munich, DE
• Wolfgang Krautschneider · Ottobrunn, DE

Key dates

• Filing date: Apr 22, 1996
• Grant date: Oct 6, 1998
• Expiry date: Apr 22, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/34

Abstract

For each storage cell, the DRAM cell arrangement has a vertical MOS transistor, the first source/drain region of which is connected to a memory node of a storage capacitor, the channel region of which is annularly enclosed by a gate electrode and the second source/drain region of which is connected to a buried bit line. The DRAM cell arrangement can be produced with a storage-cell area of 4F.sup.2 by using only two masks, F being the minimum producible structure size in the respective technology.