High speed analog flip-flop with embedded logic and phase-locked-loop circuit employing the same
US5818293A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | Oct 6, 1998 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3562
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked-loop circuit including a prescaler which divides the frequency of an output signal to thereby generate a frequency-divided signal which is provided as a feedback signal to a phase detector of the phase-locked-loop circuit. The prescaler includes a plurality of analog flip-flop circuits serially connected in a chain, with one or more outputs of latter analog flip-flop stages in the chain being fed back to one or more inputs of the first analog flip-flop. Embedded logic is integrated with the differential input pair of the first analog flip-flop to conditionally control the output of the first analog flip-flop based upon the feedback signals from the latter flip-flop stages. The analog flip-flop with embedded logic includes a master section for setting a state of a differential set up signal in response to an occurrence of a first phase of a clock signal. The master section includes a differential pair of transistors coupled to differentially control a flow current through a first and a second load during a second phase of the clock signal. First and second logic circuits are provided in the place of an input differential pair of transistors which control the flow of c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.